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COM81C17
Twenty Pin UART (TPUART)
FEATURES
! Single Chip UART With Baud Rate Generator ! Asynchronous Operation 16 Selectable Baud Rate Clock Frequencies (Internal) External 16x Clock (100 KBaud) Character Length: 7 or 8 Bits 1 or 2 Stop Bit Selection ! Small 20 Pin DIP (300 mil) or PLCC ! Full or Half Duplex Operation ! ! ! ! ! ! ! Double Buffering of Data Programmable Interrupt Generation Programmable Modem/Terminal Signals Odd or Even Parity Generate and Detect Parity, Overrun and Framing Error Detection TTL Compatible Inputs and Outputs High Speed Host Bus Operation (with no wait state) ! Low Power CMOS ! Single +5V Power Supply
GENERAL DESCRIPTION
The COM81C17 TPUART is an asynchronous only receiver/transmitter with a built in programmable baud rate generator housed in a twenty pin package. The TPUART receives serial data streams and converts them into parallel data characters for the processor. While receiving serial data, the TPUART will also accept data characters from the processor in parallel format and convert them into serial format along with start, stop and optional parity bus. The TPUART will signal the processor via interrupt when it has completely transmitted or received a character and requires service. Complete status information is available to the processor through the status register. The TPUART features two general purpose control pins that can be individually programmed to perform as terminal or modem control handshake signals.
TABLE OF CONTENTS
FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION..................................................................................................................1 PIN CONFIGURATION/TYPICAL TPUART INTERFACE.....................................................................3 BLOCK DIAGRAM ..............................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS .................................................................................................5 FUNCTIONAL DESCRIPTION ............................................................................................................6 THE ON CHIP BAUD RATE GENERATOR .........................................................................................7 REGISTER DESCRIPTIONS ..............................................................................................................8 OPERATIONAL DESCRIPTION........................................................................................................ 12
80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 273-3123
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PIN CONFIGURATION
nCP1 nINT RX RS TX
D0 nCP 2 Vcc D0 D1 nCS 18 17 16 15 14 19 13 20 1 2 3 4
nRD
D1 CLOCK D7 D6 GND D5 nCS nRD D2 D3 D4 nWR D5 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc CP2 CP1 TX RX RS nINT CLOCK D7 D6
12 11 10 5
D2
6 D3
7 D4
9 8
nWR
Package: 20 Pin PLCC
Package 20 Pin DIP
DATA BUS
D0-D7 nCP1 nCP2 DECODE nCS
ADDRESS BUS
TTL/RS-232-C
COM81C17
RS nWR nRD nINT RX TWENTY PIN UART TX
nWRITE nREAD INTERRUPT REQUEST
5.0688 MHZ FIGURE 1 - TYPICAL TPUART INTERFACE OSCILLATOR OR TTL CLOCK
FIGURE 1 - TYPICAL TPUART INTERFACE
3
D0-D7
DATA BUS TRANS
TRANSMIT BUFFER TRANSMIT SHIFT REGISTER
MODE REGISTER
TX
nCS nRD nWR RS
READ WRITE DECODE LOGIC
TRANSMIT CONTROL
INTERNAL DATA BUS
nINT
MASK REGISTER & LOGIC
BAUD RATE SELECT REGISTER
BAUD RATE GENERATOR
CLOCK
STATUS REGISTER VCC GND CONTROL REGISTER
RECEIVE CONTROL RECEIVE SHIFT REGISTER RECEIVE BUFFER RX
nCP2
nCP1
FIGURE 2 - COM81C17 BLOCK DIAGRAM
1800 OHM 560 OHM
220 OHM
7404
7404
7404
7404
220 OHM
30 pF
5.0688 MHz
FIGURE 2A - 5.0688 MHz CRYSTAL OSCILLATOR CIRCUIT
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DESCRIPTION OF PIN FUNCTIONS
DIP PIN NO. 1, 2, 5-7, 9,11-12 3 NAME DATA BUS CHIP SELECT SYMBOL DESCRIPTION D0-D7 An 8-bit bi-driectional DATA BUS is used to interface the TPUART to the processor Data Bus. nCS A low level on this input enables the TPUART for reading and writing to the processor. When nCS is high, the DATA BUS is in high impedance and the nWR and nRD will have no effect on the chip. nRD A low pulse on this input (when nCS is low) enables the TPUART to place the data or the status information on the DATA BUS. A low pulse on this input (when nCS is low) enables the TPUART to accept the data or control word from the DATA BUS into the TPUART. Power Supply Return. External TTL Clock Input (See Table 2) An interrupt request is asserted by the TPUART when an enabled condition has occurred in the Status Register. This is an active low, open drain output. This pin has an internal pullup register. During processor to TPUART communications, this input is used to indicate which internal register will be selected for access by the processor. When this input is low, data can be written to the TX Holding Buffer or data can be read from the RX Holding Register. When this input is high control words can be written to the Control Register or status information can be read from the Status Register. This input is the receiver serial data. A high to low transition is required to initiate data reception. This output is the transmitted serial data from the TPUART. When a transmission is concluded, the TX line will always return to the mark (High) state. This control pin is an input only pin. It can be programmed to perform the functions of CTS or DSR/DCD. This control pin can be programmed to be either an input or an output. When in input mode, this pin can perform the functions of DSR/DCD. When in output mode, this pin can perform the functions of DTR or RTS. +5V Supply Voltage
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READ DATA STROBE WRITE DATA STROBE GROUND CLOCK INTERRUPT REQUEST
8
nWR
10 13 14
GND CLK nINT
15
REGISTER SELECT
RS
16 17
RECEIVER DATA TRANSMITTER DATA CONTROL PIN 1
RX TX
18
nCP1
19
CONTROL PIN 2
nCP2
20
POWER SUPPLY
VCC
5
FUNCTIONAL DESCRIPTION
RESETTING THE TPUART The TPUART must be reset on power up. Since there is no external pin allocated for hardware reset, this is accomplished by writing a One (HIGH) followed by writing a Zero (LOW) to the Command Register bit 7. Following reset, the TPUART enters an idle state in which it can neither transmit nor receive data. INITIALIZING THE TPUART The TPUART is initialized by writing three control words from the processor. Only a single address is set aside for Mode, Baud Rate Select, Interrupt Mask and TX Buffer Registers. For this to be possible, logic internal to the chip directs information to its proper destination based on the sequence in which it was written. Following internal reset, the first write to address zero (i.e. RS = 0) is interpreted as a Mode Control word. The second write is interpreted as Interrupt Mask word. The third write is interpreted as Baud Rate Select. The fourth and all subsequent writes are interpreted as writes to the TX Buffer Register. There is one way in which control logic may return to anticipating a Mode, Interrupt Mask, and Baud Rate Select words. This is following an internal reset. Following initialization, the TPUART is ready to communicate. PROGRAMMABLE CONTROL PINS The TPUART provides two programmable control pins that can be configured to perform as modem or terminal control handshake signals. If no handshake signal is required, these pins can be used as general purpose one bit Input or Output ports. nCP1 - is an input only pin that can be programmed to act as the CTS (Clear To Send) handshake signal, where it will disable data transmission by the TPUART after the contents of the Transmit Shift Register is completely flushed out. When programmed as 1, nCP1 will serve as a general purpose 1 bit input port. The inverted state will be reflected in Status Register bit 0 (when programmed as CTS or general purpose input bit). nCP2 - is an Input/Output pin. When configured as Output, its state is directly controlled by the host processor via writes to the Control Register. This will serve the purpose of modem and terminal handshake signals as RTS (Reset To Send), and DTR (Data Terminal Ready). When configured as Input, its inverted state is reflected in the Status Register bit 1 and read by the processor. This will serve the purpose of handshake signals as DCD (Data Carrier Detect) and DSR (Data Set Ready).
MODE REGISTER BIT 1 0 0 1 1 BIT 2 0 1 X X nCP2 is RTS Output nCP2 is GP Output nCP2 is GP Input nCP2 is GP Input
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THE ON CHIP BAUD RATE GENERATOR The TPUART incorporates an on chip Baud Rate Generator that can be programmed to generate sixteen of the most popular baud rates. The TPUART also allows the bypassing of the Baud Rate Generator by programming Mode
Register bit 3 to accept a 16X external clock. The Baud Rate Generator will not assume any given baud rate upon power up, therefore it must be programmed as desired. The following chart is based on a 5.0688 MHz CLOCK frequency.
Table 2 - 16X CLOCK Clock Frequency = 5.0688 MHz Theoretical Actual Baud Rate Select Register D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 50 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19.200 38.400 0.8 kHz 1.76 2.152 2.4 4.8 9.6 19.2 28.8 32.0 38.4 57.6 76.8 115.2 153.6 307.2 614.4 0.8 kHz 1.76 2.1523 2.4 4.8 9.6 19.2 28.8 32.081 38.4 57.6 76.8 115.2 153.6 316.8 633.6 3.125 3.125 0.253 0.016 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 48/52 50/50 50/50 6336 2880 2356 2112 1056 528 264 176 158 132 88 66 44 33 16 8 Baud Rate Frequency 16X Clock Frequency 16X Clock Percent Error Duty Cycle % Divisor
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REGISTER DESCRIPTIONS Table 3 - COM81C17 Mode Register Description (Bits 0 - 7) BIT 0 DESCRIPTION CP1 - The Mode Register bit 0 determines whether the CP1 pin will be configured to provide the function of CTS or will serve as a general purpose 1 bit input port. In either case, its state will be reflected in Status Register bit 0. 0 nCP1 = CTS 1 nCP1 = GP INPUT CP2 I/O - The Mode Register bit 1 determines whether the CP2 pin will be configured as a general purpose 1 bit output port or will serve as a general purpose 1 bit input port. When used as an input, its state is reflected in the Status Register bit 1. When used as an output, it's state is controlled by the processor via the Control Register bit 1. 0 nCP2 = OUTPUT 1 nCP2 = INPUT CP2 - The mode register bit 2 determines whether the nCP2 pin will be configured to provide the function of RTS or will serve as a general purpose 1 bit output port. 0 nCP2 = RTS 1 nCP2 = GP OUTPUT CLOCK SELECT- The Mode Register bit 3 determines whether the internal Baud Rate Generator will supply the TX and RX clocks or the clock on the clock pin will be used as a 16X clock. The Baud Rate Select Register contents will be bypassed when an external 16X clock is used. 0 = INTERNAL CLOCK 1 = EXTERNAL CLOCK (16X) PARITY ENABLE - The Mode Register bit 4 determines whether parity generation and checking will be enabled. 0 = PARITY DISABLE 1 = PARITY ENABLE PARITY - The Mode Register bit 5 determines whether odd or even parity will be generated and checked. 0 = EVEN PARITY 1 = ODD PARITY NUMBER OF DATA BITS - The Mode Register bit 6 determines the number of data bit that will be presented in each data character (i.e. 7 or 8) 0 = 7BITS PER CHARACTER 1 = 8 BITS PER CHARACTER STOP BITS - The Mode Register bit 7 determines how many stop bits will trail each data unit (i.e. 1 or 2) 0 = 1 STOP BIT 1 = 2 STOP BITS A data frame will consist of a start bit, 7 or 8 data bits, an optional parity bit, and 1 or 2 stop bits.
1
2
3
4
5
6
7
8
BIT 0 1
2
3
4
5
6
Table 4 - COM81C17 Status Registers Description (Bits 0-7) DESCRIPTION CP1 - This reflects the inverted state of the control pin CP1. CP2 - This is active only when the nCP2 pin is programmed be to an input. It is set by its corresponding input pin and reflects the inverted state of the control pin nCP2. When the CP2 pin is programmed as an output, this bit is forced to a zero. TX SHIFT REGISTER EMPTY - This signals the processor that the Transmit Shift Register is empty. A typical program will usually load the last character of a transmission and then monitor the TX SHIFT REGISTER EMPTY bit to determine when it is a safe time for disabling transmission. This bit is set when the Transmitter Shift Register has completed transmission of a character, and no new character has been loaded in the Transmit Buffer Register. This bit is also set by asserting internal reset. This bit is cleared by: A) Loading the TX Buffer Register PARITY ERROR - This signals the processor that the character stored in the Receive Character Buffer was received with an incorrect number of binary "1" bits. This bit is set when the received character in the Receiver Buffer Register has an incorrect parity bit and parity has been enabled. This bit is cleared by: A) Setting Reset Errors in the Control Register B) Asserting internal reset OVERRUN ERROR - This is set whenever a byte stored in the Receive Character Buffer is overwritten with a new byte from the Receive Shift Register before being transferred to the processor. This bit is cleared by: A) Setting Reset Errors in the Control Register B) Asserting internal reset FRAMING ERROR - This is set whenever a byte in the Receive Character Buffer was received with an incorrect bit format ("0" stop bits). This bit is cleared by: A) Setting Reset Errors in the Control Register B) Asserting internal reset TX BUFFER EMPTY - This signals the processor that the Transmit Buffer Register is empty and that the TPUART can accept a new character for transmission. This bit is set when: A) A character has been loaded from the Transmit Buffer Register to the Transmit Shift Register B) Asserting the TRANSMIT RESET bit in the Control Register C) Asserting internal reset This bit is cleared by: A) Writing to the Transmit Buffer Register This bit is initially set when the transmitter logic is enabled by setting the TX Enable bit in the Control Register (also TX Buffer is empty because of reset). Data can be overwritten if a consecutive write is performed while TX Buffer Empty is zero.
9
BIT 7
DESCRIPTION RX BUFFER FULL - This signals the processor that a completed character is present in the Receive Buffer Register for transfer to the processor. This bit is set when a character has been loaded from the receive deserialization logic to the Receive Buffer Register. This bit is cleared by: A) Reading the Receive Buffer Register B) Asserting the RECEIVER RESET bit in the Control Register C) Asserting internal reset
BIT 0 1
Table 5 - COM81C17 CONTROL REGISTER DESCRIPTION (BITS 0-7) DESCRIPTION Not used (test mode bit, must be zero). CP2 - This bit controls the nCP2 output pin. Data at the output is the logical compliment of the register data. When the CP2 bit is set, the nCP2 pin is forced low. When CP2 is RTS, a 1 to 0 transition of the CP2 bit will cause the nCP2 pin to go high one TXc time after the last serial bit has been transmitted. RX ENABLE - This bit when reset will disable the setting of the RX BUFFER FULL bit in the Status Register which informs the processor of the availability of a received character in the Receive Buffer Register. The error bits in the Status Register will be cleared and will remain cleared when RX is disabled. RX RESET - This will reset the receiver block only. TX RESET - This will reset the transmitter block only. TX ENABLE - Data transmission cannot take place by the TPUART unless this bit is set. When this bit is reset (disable), transmission will be disabled only after the previously written data has been transmitted. RESET ERRORS - This bit when set will reset the parity, overrun, and framing error bits in the Status Register. No latch is provided in the Control Register for saving this bit; therefore there is no need to clear it (error reset = d6.RS.nWR). INTERNAL RESET - This bit enables the resetting of the internal circuitry and initializes access to address 0 to be sequential.
2
3 4 5
6
7
10
INTERRUPT MASK REGISTER DESCRIPTION This is an eight bit write only register which is loaded by the processor. These bits are used to enable interrupts from the corresponding bits in the Status Register. This register is reset with internal reset.
REGISTER DECODE & TRUTH TABLE The TPUART provides unique decode capability to three of the seven internal processor accessible register. These are the RX Buffer Register (read only), the Status Register (read only) and the Control Register (write only). The other four registers (write only) are decoded in a sequential manner following reset. Refer to table below:
RS 0 0 1 1 X
nRD 0 1 0 1 X
Table 6 - DECODE TRUTH TABLE nWR nCS 1 0 1 0 X 0 0 0 0 1 READ RX BUFFER REGISTER WRITE TO TX BUFFER REGISTER READ STATUS REGISTER WRITE TO CONTROL REGISTER DATA BUS IN TRI STATE Following reset, the decode sequence of writes to address 0 is as follows: RS0 - Selects the Mode Control Register RS1 - Selects the Interrupt Mask Register RS2 - Selects the Baud Rate Select Register RS3 - Selects the TX Buffer Register
The first write to address zero (RS = 0) will access the Mode Register, the second will access the Interrupt Mask Register, the third will access the Baud Rate Select Register, the fourth and all subsequent writes will access the TX Buffer Register.
RS0 0 1 1 1 1
Table 7 - INTERNAL REGISTER SELECT RS1 RS2 RS3 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 AFTER RESET AFTER FIRST WRITE AFTER SECOND WRITE AFTER THIRD WRITE ALL SUBSEQUENT WRITES
11
OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range......................................................................................... 0 C to +70 C o o Storage Temperature Range .......................................................................................... -55 to +150 C o Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 C Positive Voltage on any pin ..................................................................................................... Vcc+0.3V Negative Voltage on any pin, with respect to ground ................................................................... -0.3V Maximum VCC ................................................................................................................................ +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. Table 8 - ELECTRICAL CHARACTERISTICS o o T = 0 C to +70 C, VCC = +5.0V 5% PARAMETER SYMBOL MIN TYP MAX UNITS LOW INPUT VOLTAGE HIGH INPUT VOLTAGE LOW OUTPUT VOLTAGE HIGH OUTPUT VOLTAGE INPUT LEAKAGE CURRENT INPUT CAPACITANCE POWER SUPPLY CURRENT VIL VIH VOL VOH IL CIN ICC 10 15 2.4 10 2.0 0.4 0.8 V V V V A pF ma IOL = 5.0ma D0 - D7 IOL = 3.5ma IOH = 100a
o o
COMMENTS
12
Table 9 - AC CHARACTERISTICS SYMBOL DESCRIPTION MIN TYP MAX UNITS
AC CHARACTERISTICS WRITE CYCLE t1 t2 t3 t4 t5 READ CYCLE t6 t7 t8 t9 t10 GENERAL TIMING t11 t12 t13 t14 t15 nCP1, nCP2 data Rise Time Fall Time CLOCK FREQUENCY Rise Time Fall Time Internal Baud Rate Mode External Baud Rate Mode Duty Cycle 30 30 11.0 1.6 40/60 ns ns MHz MHz % 30 30 ns @25pf ns @25pf Reset Pulse Width nCP1 active to nINT nWR rising edge to nCP2 change CP1, CP2 pulse width Read Write Interval 1.0 100 1.0 300 200 s s @25pf s s ns nCS, RS to nWR setup time nCS, RS hold time to nWR nWR pulse width Data BUS in setup time to nWR Data BUS in hold time to nWR nCS, RS to nWR setup time nCS, RS hold time to nWR nWR pulse width Data BUS in setup time to nWR Data BUS in hold time to nWR 50 0 100 75 10 50 0 100 0 0 60 60 ns ns ns ns ns ns ns ns ns @50pf max ns @50pf max
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nCS
RS t1 nWR t2
t3
t4 DIN
t15 t5
FIGURE 3 - PROCESSOR TO TPUART WRITE CYCLE
nCS
RS t6 nRD t7
t8
t9 t10 DOUT valid data
t15
FIGURE 4 - PROCESSOR FROM TPUART READ CYCLE
14
t11 nWR TO CONTROL REGISTER
D7IN
INTERNAL RESET
FIGURE 5 - INTERNAL RESET TIMING
nCP1 nCP2 t12 nINT
FIGURE 6 - nCP1 TRANSITION TO nINT
15
nWR t13
nCP2
FIGURE 7 - nCP2 OUTPUT TIMING
nCP1 nCP2
t14
FIGURE 8 - nCP1, nCP2 INPUT TIMING
16
17
81988 STANDARD MICROSYSTEMS CORP.
Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. SMSC reserves the right to make changes at any time in order to improve design and supply the best product possible. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer.

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